For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.
Non-volatile embedded memory with MRAM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of patterning MRAM devices present formidable roadblocks to commercialization of this technology today. Specifically alignment of MRAM devices onto interconnects with exceedingly small dimensions and pitch sizes, etching MRAM devices without adversely impacting the underlying materials or the device itself are some important areas of process development.
As such, significant improvements are still needed in the area of non-volatile memory integration based on MRAMs.